Title page for etd-1121117-102836


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URN etd-1121117-102836
Author Wen-Chih Li
Author's Email Address No Public.
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Department Institute of Medical Science and Technology
Year 2017
Semester 1
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Analog Front-end Circuits and Time-Frequency Analysis Design for ECG Sensing System
Date of Defense 2017-12-20
Page Count 116
Keyword
  • front-end circuit
  • sliding discrete Fourier transform
  • Instrumentation amplifier
  • Abstract Recently, the demand for wireless electronic medical devices has been greatly increased. The innovation of wearable sensors with a portable data analysis device can not only monitors medical parameters of the patient under the less affection to human’s daily activities. Based on above design target, we design several chips for the implementation of the measuring and analyzing platform which includes the following three parts: (1) A front-end readout circuit is composed of Instrumentation Amplifier (IA), band-pass filter, gain stage, and Analog-to-Digital Converter (ADC); (2) A digital signal processor on Field-Programmable Gate Array (FPGA) is responsible for handling the convolution operation of Hanning window; (3) A back-end analysis circuit is composed of sliding discrete Fourier transform (SDFT);
    The operational steps for the proposed platform are as follow: (1) we convert electrocardiogram (ECG) signals to digital codes through the front-end circuit; (2) the processor on FPGA will deal with the ECG digital codes by multiplying the cefficients of Hanning window; (3) the time-domain ECG digital codes are converted into the spectrum results through the SDFT circuit, and then the time-frequency analysis is achieved.
    The proposed design is realized by using TSMC CMOS 0.18-µm technology. The proposed IA has 89dB CMRR and 88dB PSRR. Under a 1-kHz sampling rate, the SNDR and ENOB of the proposed SAR ADC are 58.8dB and 9.4bit. The chip area and total power consumption of analog circuit chip area are 1.599X1.146mm2, and 0.238mW, respectively. Under a 1-kHz operating frequency, the gate count, chip area, and power consumption of the proposed time-frequency processor are 73446, 1.151X1.141mm2, and 1.62μW, respectively. The time-frequency module compared with Krzysztof Duda’s method, the number of multiplication and addition are achieve 80.35% and 54.91% reducing, respectively. Therefore, the proposed platform can achieve low-complexity and area effectively. We believe it can help us to develop a portable and low-power detecting device in the future.
    Advisory Committee
  • Shin-Chi Lai - chair
  • Wen-kai Tsai - co-chair
  • Yuan-Pin Lin - advisor
  • Ching-Hsing Luo - advisor
  • Files
  • etd-1121117-102836.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2017-12-21

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