Title page for etd-1115115-082713


[Back to Results | New Search]

URN etd-1115115-082713
Author Yi-Chieh Chen
Author's Email Address ycchen@esl.cse.nsysu.edu.tw
Statistics This thesis had been viewed 5575 times. Download 95 times.
Department Computer Science and Engineering
Year 2015
Semester 1
Degree Master
Type of Document
Language English
Title A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches
Date of Defense 2015-10-23
Page Count 68
Keyword
  • Fault-Tolerant
  • Microprocessor
  • Memory
  • Fault Injection
  • Fault Coverage
  • Abstract We present an integrated development environment (IDE) with GUI for generating and evaluating the fault-tolerant microprocessor. Designer can select from hardware options (dual-core for microprocessor, error detection code or error correction code for memory) and automatically generates configuration file for RTL code. In addition, the application can be encoded by our Analyzer and generate signature augmented program to detect the control-flow error in the run-time. In the end, it also performs simulation-based fault injection campaign to evaluate the fault detection capabilities of different fault-tolerant configurations. The IDE and GUI have been implemented for Andes N801s microprocessor core. This workbench would also provide estimated performance, cost overheads and fault coverage for the generated fault-tolerant architecture in order to suite different safety level applications or user requirements.
    Advisory Committee
  • Chung-Ho Chen - chair
  • Qi-Feng Wu - co-chair
  • Xin-Yu Shih - co-chair
  • Fu-Ching Yang - co-chair
  • Yeong-Kang Lai - co-chair
  • Ing-Jer Huang - advisor
  • Files
  • etd-1115115-082713.pdf
  • Indicate in-campus at 3 year and off-campus access at 3 year.
    Date of Submission 2015-12-23

    [Back to Results | New Search]


    Browse | Search All Available ETDs

    If you have more questions or technical problems, please contact eThesys