Title page for etd-1027114-184928


[Back to Results | New Search]

URN etd-1027114-184928
Author Chun-Hung Lai
Author's Email Address No Public.
Statistics This thesis had been viewed 5356 times. Download 194 times.
Department Computer Science and Engineering
Year 2014
Semester 1
Degree Ph.D.
Type of Document
Language English
Title A Versatile Cache Architecture for Better Utilization of the Cache Space
Date of Defense 2014-10-24
Page Count 151
Keyword
  • Trace Compression
  • Trace Storage
  • Multi-Role Cache
  • Cache Tag Arrays
  • Reconfigurable Cache
  • SPM
  • Cache
  • Abstract Larger on-chip cache design is a clear design trend for general purpose systems to accommodate different characteristics in ever diversifying developments and applications of modern SoC’s. While larger caches are effective for a wide range of the conventional workloads, whereas such design philosophy is inadequate for workloads that benefit little from large caches. Its consequence is that the underutilized cache space consumes power constantly without any contribution. Though many research efforts have been attempted to build some flexibility in the cache to adapt the behavior of different applications, most of these studies take only the cache data arrays into account but the cache tag arrays are not considered. In this thesis, we propose a versatile cache architecture on which the underutilized portion of cache can be organized in different ways other than the conventional caching. First, the instruction cache is reused to perform real time program trace compression without incurring any additional cache misses. Second, the data cache can be configured as a trace bufferer for monitoring and debugging support and is protected from regular cache operations. Finally, the unused cache tag arrays can be transformed as the extension of SPM while the corresponding cache ways are configured as other types of functional units (SPM or buffers/lookup tables). The integration of the proposed versatile cache architecture with an academic ARM general purpose processor, and a programmable shader 3D graphics (3DG) SoC has been accomplished at RTL, FPGA, and chip levels to prove its feasibility and effectiveness. The results show that the hardware overhead is very minor, TC cache and DT cache have only 3.652K gates and 2.383K gates, only 0.123% and 0.081% overhead respectively to a modern SoC. In addition, the required support circuit and cache modification do not impair the global critical path delay. Therefore, the proposed approaches are highly feasible solutions for exploring a diversity of cache functionalities. Furthermore, both the cache data and tag arrays are taken into consideration for the efficient cache utilization.
    Advisory Committee
  • Chia-Lin Yang - chair
  • Guang-Zhi Liu - co-chair
  • Chi-Feng Wu - co-chair
  • Fu-Ching Yang - co-chair
  • Shen-Fu Hsiao - co-chair
  • Ing-Jer Huang - advisor
  • Files
  • etd-1027114-184928.pdf
  • Indicate in-campus at 1 year and off-campus access at 1 year.
    Date of Submission 2014-11-27

    [Back to Results | New Search]


    Browse | Search All Available ETDs

    If you have more questions or technical problems, please contact eThesys