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URN etd-1020109-194529
Author Ming-Yu Tsai
Author's Email Address mjtsai@garfield.cse.nsysu.edu.tw
Statistics This thesis had been viewed 5345 times. Download 1793 times.
Department Computer Science and Engineering
Year 2009
Semester 1
Degree Ph.D.
Type of Document
Language English
Title An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors
Date of Defense 2009-10-19
Page Count 141
Keyword
  • 3D Graphics Processors
  • Arithmetic Units
  • Standard Cell Library
  • ASIC Cell-Based Design Flow
  • Logic Synthesizer
  • Pass-Transistor-Logic (PTL)
  • CMOS logic
  • Abstract The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. Compared with CMOS circuits, these PTL-based circuits are claimed to have better results in area, speed, and power in some particular applications, such as adder and multiplier designs. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this dissertation, we develop two novel PTL synthesizers that can efficiently generate PTL-based circuits. One is based on pure PTL cells; the other mixes CMOS and PTL cells in the standard cell library to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated to design large SoC systems as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flows employ the popular Synopsys Design Compiler (DC) to perform logic translation and minimization based on the standard cell library composed of PTL and CMOS cells, thus, the PTL design flow can be easily embedded in the standard cell-based ASIC design flow. In this dissertation, we also discuss PTL-based designs of some fundamental hardware components. Furthermore, the proposed PTL cell library is used to synthesize large processor systems in applications of computer arithmetic and 3D graphics.
    Advisory Committee
  • Bin-Da Liu - chair
  • Chen-Hao Chang - co-chair
  • Yuan-Sun Chu - co-chair
  • Pei-Yin Chen - co-chair
  • Yu-Jung Huang - co-chair
  • Tso-Bing Juang - advisor
  • Shen-Fu Hsiao - advisor
  • Files
  • etd-1020109-194529.pdf
  • indicate accessible in a year
    Date of Submission 2009-10-20

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