Title page for etd-1012109-151215


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URN etd-1012109-151215
Author Fu-Ching Yang
Author's Email Address No Public.
Statistics This thesis had been viewed 5583 times. Download 1414 times.
Department Computer Science and Engineering
Year 2009
Semester 1
Degree Ph.D.
Type of Document
Language English
Title SYS-SIP SoC Development Infrastructure
Date of Defense 2009-09-24
Page Count 146
Keyword
  • SoC development
  • Debug
  • Verification
  • Monitoring
  • External interrupt
  • Abstract System-on-a-Chip (SoC) is a trend to achieve high performance, low cost, and low power in modern electronic devices. As the demand of functionality and performance increase, more IPs (Intellectual Property) are integrated into a modern SoC. Developing such a complex SoC is challenging since the SoC has limited observability; modern SoCs usually leave limited spared I/O pins for debugging purpose due to cost consideration, making it hard to analyze the internal activities via the limited I/O pins. This hampers the SoC development. To ease the difficulty, we have implemented the SYS-SIP (National Sun Yat-Sen university's SoC Infrastructure IP's) to enable the SoC development in terms of verification, debugging, monitor
    ing, and performance tuning. The SYS-SIP consists of five members: Processor External Interrupt Verification Module (PEVM), ICE, processor tracer, bus tracer, and protocol checker. Each of them serves specific purposes in verification, debugging, monitoring, and performance tuning. The SYS-SIP can be applied at diffierent design stages: RTL, FPGA, and chip level. The results show that SYS-SIP eases the SoC development and shortens the time-to-market significantly.
    Advisory Committee
  • Chua-Ching Wang - chair
  • Cheng-Wen Wu - co-chair
  • Jing-Yang Jou - co-chair
  • Kuen-Jong Lee - co-chair
  • Jiun-In Guo - co-chair
  • Ing-Jer Huang - advisor
  • Files
  • etd-1012109-151215.pdf
  • indicate in-campus access immediately and off_campus access in a year
    Date of Submission 2009-10-12

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