Title page for etd-1012101-091101


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URN etd-1012101-091101
Author Yi-Chang Chen
Author's Email Address arnor@jasmine.ee.nsysu.edu.tw
Statistics This thesis had been viewed 5598 times. Download 8685 times.
Department Electrical Engineering
Year 2001
Semester 1
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title The Study of Double Level Branch Buffer
Date of Defense 2001-10-09
Page Count 62
Keyword
  • Pipelining
  • Branch Penalty
  • Branch Prediction
  • Branch Target Buffer
  • Abstract  Pipelining is the major organizational technique by which computers can execute several instructions simultaneously to reach higher single-processor performance. Branches are recognized as a major impediment to achieve the maximum performance of pipelining and superscalar processors due to stalls caused by unresolved branches. Branch prediction is an effective strategy to reduce the branch penalty via predicting, prefetching and executing the speculative instructions before the branch is resolved. A branch target buffer (BTB)[13] can reduce the performance caused by branches via predicting the direction of the branch and caching information about the branch. While prediction is incorrect, the processor requires flushing the speculative instructions, undoing the effects of the improperly initiated speculative execution and resuming on the correct path. These flushing and refilling degrade significantly processor performance.
     In this thesis we propose a mechanism, Double Level Branch Buffer, which can reduce the branch penalty and performance loss caused from incorrect prediction. We try to cache the information of branch about both taken and not taken direction. The pipeline will degrade the dependence upon branch prediction accuracy by utilizing this mechanism.
    Advisory Committee
  • Shie-Jue Lee - chair
  • Chu-Sing Yang - co-chair
  • Wen-Shyong Hsieh - co-chair
  • Tsung-Chuan Huang - advisor
  • Files
  • etd-1012101-091101.pdf
  • indicate access worldwide
    Date of Submission 2001-10-12

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