Title page for etd-1005105-143759


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URN etd-1005105-143759
Author Ming-Chih Chen
Author's Email Address No Public.
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Department Computer Science and Engineering
Year 2005
Semester 1
Degree Ph.D.
Type of Document
Language English
Title Low Cost Design of Advanced Encryption Standard (AES) Algorithm Using Efficient Common Sub-expression Elimination Methods
Date of Defense 2005-09-21
Page Count 96
Keyword
  • Logic Optimization
  • AES
  • VLSI
  • Abstract In this dissertation, we propose area-efficient Advanced Encryption Standard (AES) processor designs by applying four new common-subexpression-elimination (CSE) algorithms to the sub-functions that realize the various transformations in AES encryption and decryption. The first category of sub-functions is derived by combining adjacent transformations in each AES round into a new transformation. The other category of sub-functions is from the integrated transformations in the AES encryption and decryption process with shared common operations. Then the proposed bit-level CSE algorithm reduces further the area cost of realizing the sub-functions by extracting the common factors in the bit-level expressions of these sub-functions. The separate area-reduction effects of combinations, integrations and CSE optimization mentioned above are analyzed in order to examine the efficiency of each technique. Cell-based implementation results show that the area reduction rates of the AES processors with our proposed CSE methods achieve significant area improvement compared with Synopsys optimization results.
    Advisory Committee
  • Bin-Da Liu - chair
  • Jau-Der Shih - co-chair
  • Chua-Chin Wang - co-chair
  • Ming-Hwa Sheu - co-chair
  • Jiun-In Guo - co-chair
  • Shen-Fu Hsiao - advisor
  • Files
  • etd-1005105-143759.pdf
  • indicate in-campus access in a year and off_campus not accessible
    Date of Submission 2005-10-05

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