Title page for etd-0911108-201039


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URN etd-0911108-201039
Author Shang-da Yang
Author's Email Address No Public.
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Department Electrical Engineering
Year 2007
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Implementation of Hierarchical Architecture of Basic Memory Modules
Date of Defense 2008-07-24
Page Count 37
Keyword
  • system-on-chip
  • memory
  • memory interface
  • memory controller
  • Abstract In system-on-chip designs, memory designs store data to be accessed by processing modules. Memory access time can affect overall system performance significantly. In this research, we implemented a configurable architecture of a basic memory module and its design composition, including memory interface, memory controller, memory array, row buffer, row decoder and column decoder. We explore various memory module designs. Utilizing the configurable architecture, we can effectively reduce design time and improve access time of memory module designs. We also realized these functionalities in SystemC language and performed configurability experiments.
    Advisory Committee
  • Chia-Hsiung Kao - chair
  • Chih-Chien Chen - co-chair
  • Tsung Lee - advisor
  • Files
  • etd-0911108-201039.pdf
  • indicate accessible in a year
    Date of Submission 2008-09-11

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