Title page for etd-0911108-192726


[Back to Results | New Search]

URN etd-0911108-192726
Author Feng-yuan Liu
Author's Email Address No Public.
Statistics This thesis had been viewed 5565 times. Download 1535 times.
Department Electrical Engineering
Year 2007
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Implementation of Hierarchical Architecture of Advanced Functionality of Memory Modules
Date of Defense 2008-07-24
Page Count 63
Keyword
  • fault tolerant
  • memory
  • silicon intellectual properties
  • system on chip
  • Abstract Due to advancement of semiconductor technology, a system can be designed in a single chip, we call it a system on chip (SOC). An SOC usually reuses silicon intellectual properties (SIP). This speeds up design time and increase correctness of the chip. Memory modules play an important role in an SOC. Under various system requirements, different memory modules should be used. In this research, in order to satisfy various design requirements of memory modules, we designed various advanced and application-specific functional features to be added into memory modules. We planed a configuration method and implemented needed component designs, including fault tolerance, encryption, and allocation. Hence, we can speed up design time and increase design correctness of such memory module designs.
    Advisory Committee
  • Chia-Hsiung Kao - chair
  • Chih-Chien Chen - co-chair
  • Tsung Lee - advisor
  • Files
  • etd-0911108-192726.pdf
  • indicate accessible in a year
    Date of Submission 2008-09-11

    [Back to Results | New Search]


    Browse | Search All Available ETDs

    If you have more questions or technical problems, please contact eThesys