Title page for etd-0905111-175934


[Back to Results | New Search]

URN etd-0905111-175934
Author Yi-Dai Huang
Author's Email Address No Public.
Statistics This thesis had been viewed 5341 times. Download 305 times.
Department Computer Science and Engineering
Year 2010
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Smart Buffer Management Architecture of 3D Graphic Rendering System
Date of Defense 2011-07-28
Page Count 78
Keyword
  • Rendering System
  • Depth Buffer
  • Buffer Clear
  • 3D Graphics
  • Depth Compression
  • Abstract This thesis presents an efficient buffer management scheme for 3-D graphic rendering systems. The purpose of this scheme is to reduce the off-chip memory accesses, which have become a valuable resource, and very often a performance bottleneck of embedded 3-D applications. The 3-D buffers, including depth and color frame buffers, will be divided into rectangular blocks. The proposed scheme can first provide the management of buffer clear operation. For most of time, the rendering of each 3-D frame starts from the buffer clear command to clear the data remaining in buffers from the previous frame. Instead of clearing the buffers residing in the off-chip memory immediately, our scheme will just set the clear flag in an on-chip buffer management table which provides a control information entry for each of the blocks in the buffer. When the blocks have to be accessed later during rendering process, they won’t be brought in from on-chip memory; instead, they are cleared directly in the corresponding cache location. When the cache blocks are replaced, the corresponding off-chip buffer blocks will be updated. Only those blocks in the off-chip color buffer which are not visited will be actually cleared when the color frame is swapped for display. The second contribution of the propose management scheme is to compress and decompress the depth blocks to save the transfer data amount of these blocks. Since the difference of the depth values of the neighboring pixels belonging to the same triangle plane will be the same, this difference value can be stored and encoded along with the run-length information which can lead to significant saving of the storage space. The actual reduction ratio depends on the relative object complexity to the output screen size, the block size, and the degree of the anti-aliasing considered. However, our experimental results show that the compression ratio of 17-28% can be achieved for the moderate block size. The entire buffer management has been implemented, and the entire gate count is 65k, which is about 10% of the entire 3-D systems. The proposed management chip is very suitable for embedded 3D graphic rendering systems where the memory bandwidth budget is very tightly restricted.
    Advisory Committee
  • Shen-Fu Hsiao - chair
  • Shian-Rung Kuang - co-chair
  • Yun-Nan Chang - advisor
  • Files
  • etd-0905111-175934.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2011-09-05

    [Back to Results | New Search]


    Browse | Search All Available ETDs

    If you have more questions or technical problems, please contact eThesys