Title page for etd-0901110-122544


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URN etd-0901110-122544
Author Chih-hung Chen
Author's Email Address No Public.
Statistics This thesis had been viewed 5569 times. Download 6 times.
Department Electrical Engineering
Year 2010
Semester 1
Degree Master
Type of Document
Language English
Title 1MHz Bandwidth Switched-Current Sigma Delta Modulator
Date of Defense 2010-08-27
Page Count 83
Keyword
  • delta-sigma modulator
  • sigma-delta modulator
  • switched-current circuit
  • integrator
  • sample and hole
  • current comparator
  • Abstract The thesis proposes an integrator with an OPAMP in the feedback loop to fulfill 1MHz bandwidth SI Sigma Delta modulator. The OPAMP is used to pull down the input impedance and get high speed and high resolution. Oversampling and noise shaping are the two keys of Sigma Delta modulator. In structure, multistage is helpful for depressing noises and we use three stages to fulfill this 4-order proposed Sigma Delta modulator. 
    The proposed Sigma Delta modulator uses TSMC 0.18μm CMOS process and it is a 4-order and three stages SI Sigma Delta modulator. The sampling rate is 32MHz, bandwidth is 1MHz, and oversampling ratio is 16.
    Advisory Committee
  • Tzu-sheng Hung - chair
  • Ko-chi Kuo - co-chair
  • Chia-hsiung Kao - advisor
  • Files
  • etd-0901110-122544.pdf
  • indicate in-campus access in a year and off_campus not accessible
    Date of Submission 2010-09-01

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