Title page for etd-0831110-160513


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URN etd-0831110-160513
Author Cheng-Han Lee
Author's Email Address pp888168@gmail.com
Statistics This thesis had been viewed 5360 times. Download 3214 times.
Department Computer Science and Engineering
Year 2009
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Design, Analysis and Applications of Hybrid CORDIC Processor Architectures
Date of Defense 2010-07-14
Page Count 145
Keyword
  • Arithmetic Function Units
  • CORDIC
  • Taylor-series expansion
  • Abstract In this thesis, we propose different CORDIC architectures which solve the problems of long-latency in traditional pipeline CORDIC and the large-area cost in table-based CORDIC. The original table-based CORDIC can be divided into two stages, coarse stage and fine stage. We also propose the three-stage architectures, composed of traditional pipeline CORDIC, Rom/Multiplier architecture and linear approximation. Detailed analysis and estimation in area and latency of these different two-stage and three-stage architectures with different bit accuracy are given in order to determine the best architecture design for a particular precision. Finally, we choose one of the architectures to implement, compare the results, and show its applications.
    Advisory Committee
  • Chuen-Yau Chen - chair
  • Tso-Bing Juang - co-chair
  • Shiann-Rong Kuang - co-chair
  • Shen-Fu Hsiao - advisor
  • Files
  • etd-0831110-160513.pdf
  • indicate access worldwide
    Date of Submission 2010-08-31

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