|Author's Email Address
||This thesis had been viewed 5567 times. Download 723 times.|
|Type of Document
||Third Order Continuous-Time Sigma-Delta Modulator with 1.5bit Quantizer|
|Date of Defense
||The thesis proposes a third order continuous-time sigma delta modulator used in GSM. We used a special 1.5bit quantizer, and to use its three different states to reach a differential feedback path. That can improve the resolution of our circuit.|
Oversampling and noise shaping are two keys of sigma delta modulator. In structure, the continuous-time features can reduce power consumption.
The proposed sigma delta modulator uses TSMC 0.35 m CMOS process and its sampling frequency is 10.8MHz, bandwidth is200KHz and oversampling ratio is 32.
||Tzyy-Sheng Horng - chair|
Ko-Chi Kuo - co-chair
Jyi-Tsong Lin - advisor
Chia-Hsiung Kao - advisor
Indicate in-campus at 5 year and off-campus access at 5 year.|
|Date of Submission