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|| Materials and Optoelectronic Science|
|Type of Document
||Development of high efficieny CdTe thin-film solar cell|
|Date of Defense
||CdTe films were deposited by sputtering technique and were then carried out by CdCl2 treatment. The SEM micrographs show that the grain sizes of the as-deposited CdTe film were normally ranged from 50 nm to 100 nm, and they were recrystallized after CdCl2 treatment to obtain the grain sizes in the range of 1~3 μm.|
A new device structure for CdTe thin-film solar cells has been proposed to exceed the cell efficiency of current record. The superstrate structure with the layer sequence of Glass/AZO/ZnO/CdS/CdTe/CI(G)S/Mo compared with the conventional device structure of Glass/FTO/CdS/CdTe/metal contact would have the following advantages:(1) a highly conductive AZO layer combined with a thin undoped ZnO layer will have higher optical transmission than that of FTO; (2) the use of p-type CIS under the CdTe layer with the same conductivity type can extend the light absorption to longer wavelength range (the band gaps of CdTe and CIS are 1.45eV and 1.04eV, respectively); (3) the proper addition of Ga to CIS may form CIGS quaternary compounds with a bandgap gradient which produce an electric field in the neutral region of a p-n junction to reduce the carrier recombination; (4) the use of Mo contact to CI(G)S is quite stable as compared with the metal contact normally used for p-CdTe. AMPS-1D simulation had been applied to evaluate the newly designed device structure and the results indicated a great improvement in device performance, i.e. the cell efficiency could exceed 20%.
The I-V curve of a CdTe solar cell using the new device structure showed a nearly linear characteristic indicating the failure to form a p-n junction. We speculated that Cu might diffuse through the CdTe layer to the depletion region of the p-n junction formed at the CdS/CdTe interface. This would cause the junction failure. Based on the calculation on the Cu diffusion during the deposition of CIS layer at different temperatures even as low as 150˚C, it always had the chance to diffuse through the CdTe layer.
An alternate device fabrication process was the use of the substrate structure for preparing CdTe solar cells, i.e. Glass/Mo/CIS/CdTe/CdS/ZnO/AZO/Al. However, the desired diode behavior was not observed until the thickness of CdTe layer was cut down to 10 nm. The electrical properties of that particular solar cell is the following:Voc=0.36V, Isc=4.991mA/cm2, F.F.=25.3%, efficiency=0.472%. It is probably that the lattice mismatch between CIS and CdTe is large that may cause the formation of interfacial defects and the reduction of photo excited carriers through the recombination processes. The annealing processes had been conducted in order to promote the interdiffusion between CdTe and CIS and minimize the lattice mismatch. However, the films peered off after annealing. Further experiments should be done to solve this problem.
||Mau-phon Houng - chair|
Tsung-ming Tsai - co-chair
Bae-heng Tseng - advisor
Indicate in-campus at 99 year and off-campus access at 99 year.|
|Date of Submission