Title page for etd-0824111-172556


[Back to Results | New Search]

URN etd-0824111-172556
Author Po-Yu Ku
Author's Email Address bodecenty@gmail.com
Statistics This thesis had been viewed 5350 times. Download 1087 times.
Department Electrical Engineering
Year 2010
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title The Optimal Design for Face Detection Algorithm on Cell Processor Architecture
Date of Defense 2011-07-19
Page Count 73
Keyword
  • Multiple Buffering
  • Modified Census Transform (MCT)
  • SIMD
  • Synergistic Processor (SPE)
  • Heterogeneous
  • PowerPC Processor Element (PPE)
  • Abstract With the advance of facial recognition technology, many related applications such as the clearance of specific facilities, air port security, video camera surveillance, and personnel recognition. To maximize working efficiency and reduce human resource, the platform used for facial recognition should possess both low cost, multimedia performance, and the ease of use. Among the list of available platforms, a IBM CELL multi-core based platform that features the aforementioned advantages is used to manifest our work. To meet the demand of recognition accuracy, a recognition algorithms using features low error rate and regular data patterns are adopted. These algorithms are carried out in two parts: Modified Census Transform (MCT) and hypotheses of human facial calculation. The multi-point average value required by the MCT is obtained through parallel processing, and potential improvement in recognition efficiency is possible if wider data paths are used. A PlayStation 3 (PS3) platform equipped with the IBM CELL multi-core processor is used in this thesis. The IBM CELL multi-core processor consists of a PowerPC Processor Element (PPE) and 8 Synergistic Processor (SPE), which forms a heterogeneous multi-core system. This system is capable of parallelizing thread-level and data-level data words, which can meet the demand of high data bandwidth and data parallelization. By using this platform to accelerate the processing of facial recognition, simulation results suggest that the execution efficiency is improved by 24 times when compared with a single core SPE. The simulation also reveals that the use of parallelization of processing facial recognition data feasible. In the future, improved algorithms can be applied to improve the accuracy of facial recognition.
    Advisory Committee
  • Chung-Ping Chung - chair
  • Chia-Hung Yeh - co-chair
  • Wann-Yun Shieh - co-chair
  • Jih- Ching Chiu - advisor
  • Files
  • etd-0824111-172556.pdf
  • indicate access worldwide
    Date of Submission 2011-08-24

    [Back to Results | New Search]


    Browse | Search All Available ETDs

    If you have more questions or technical problems, please contact eThesys