Title page for etd-0821100-150631


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URN etd-0821100-150631
Author Chung-Fu Kao
Author's Email Address cfkao@cadal.cse.nsysu.edu.tw
Statistics This thesis had been viewed 5582 times. Download 1974 times.
Department Computer Science and Engineering
Year 1999
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Exploration of Multiple ICE’s for Embedded Microprocessor Cores in an SOC
Date of Defense 2000-07-28
Page Count 62
Keyword
  • SOC
  • IP
  • ICE
  • Abstract SOC (System-On-Chip) designs are more and more popular, concurrently, more and more new challenges system integrators will meet. One out of these challenges is testing problem. Our research is focus on how to testing and debugging the microprocessor cores that embedded in an SOC. Not only test the microprocessor cores but also test the interconnecting wire among these embedded microprocessor cores. This thesis explores architectural alternatives in the integration of embedded in-circuit emulation (ICE) into an SOC chip with multiple micro-controller/processor cores. The alternatives include distributed, centralized and hierarchical styles. Advantages and disadvantages of these alternatives are analyzed.
    Advisory Committee
  • Chung-Ho Chen - chair
  • James Kuo - co-chair
  • Min-hon Jing - co-chair
  • Juinn-Dar Huang - co-chair
  • Ing-Jer Huang - advisor
  • Files
  • 碩士論文.pdf
  • indicate access worldwide
    Date of Submission 2000-08-21

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