|Author's Email Address
||This thesis had been viewed 5371 times. Download 2180 times.|
||Computer Science and Engineering|
|Type of Document
||Power Optimization for 3D Vertex Shader Using Clock Gating|
|Date of Defense
3D vertex shader
||With technology increasingly and the needs of high performance and multiple functionalities, power dissipation has be a bottleneck in microprocessors. And clock power is the most percentage of total power dissipation. In our thesis, we will provide an effective clock gating methodology that has not more overhead possibly to decrease total power dissipations based on SIMD 3D vertex shader. Except for classify all instructions according the instruction flow, we also consider the relationship of pipeline stage and are based on register bank to control execution units more flexibility.|
Using clock gating not only can decrease clock power, but also decrease the power of hardware modules succeed the registers with clock gating that be controlled. In our thesis, we will analysis which clock gating version is suitable because there is not definitely to disable the clock of all pipeline registers of all pipeline stages and hold all opportunities that can disable the clock. We will explain on experimental results and show the final low power version.
With experimental results, the clock gating methodology that we bring can decrease almost 30% power with increase less than 2% area. And collection of instruction schedule algorithm for high performance that can decrease 41% energy at most. In new version of four vertexes execute sequentially, using clock gating can also decrease almost 10% power dissipation. And collection of instruction schedule algorithm for this version not only has better performance result but also can decrease 16% energy at most.
||Jer-Min Jou - chair|
Ko-Chi Kuo - co-chair
Pei-Yin Chen - co-chair
Shiann-Rong Kuang - advisor
indicate accessible in a year|
|Date of Submission