|Author's Email Address
||This thesis had been viewed 5350 times. Download 411 times.|
|Type of Document
||Design of One-Time Implantable SCS System SOC and Inter-chip Capacitance Coupling Circuit|
|Date of Defense
|| bidirectional communication
high-speed data transceiver
||The thesis is composed of two topics: A SOC design for one-time implantable spinal cord stimulation system （SCS）, and the design of an inter-chip capacitance coupling circuit. |
In the first topic, the SOC design using wireless power and data transmission techniques for the SCS system is presented in this work. The proposed SOC can control 4 electrodes to generate different patterns of stimulation waves. It has multiple modes to drive whole the SCS system. Notably, the SOC contains a novel ASK demodulator which converts the ASK signals into digital signals reliably. The SOC is implemented using a typical 0.18-μm 1P6M CMOS process. The chip area is only 1.71 * 1.41 mm2. Besides, the volume of the implantable SCS pulse generator utilizing this SOC is less than 24 cm3, and the power consumption is only 59.4 mW.
In the second topic, a high-speed inter-chip capacitance coupling circuit is presented. Digital signals between two chips can be transceived through capacitive coupling of the proposed circuit. Notably, the transceivers are designed below the capacitors to attain the area reduction. It is an advanced application for high-speed wafer testing and 3D IC communication. A prototype chip is presented to achieve 2 Gbps on silicon using a typical 0.18 μm 1P6M CMOS process. The chip area is 1045 × 894 μm2. Besides, it only costs 21.47 mW in terms of power consumption. This capacitive coupling technique for high-speed digital circuit has great potential in the coming future.
||Sying-Jyan Wang - chair|
Soon-Jyh Chang - co-chair
Shen-Fu Hsiao - co-chair
Chua-Chin Wang - advisor
Indicate in-campus at 0 year and off-campus access at 5 year.|
|Date of Submission