Title page for etd-0814117-182647


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URN etd-0814117-182647
Author Yi-Hsuan Huang
Author's Email Address No Public.
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Department Computer Science and Engineering
Year 2017
Semester 1
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System
Date of Defense 2017-09-14
Page Count 94
Keyword
  • , PLC
  • FFT
  • QAM
  • Interleaver
  • Scramble
  • Turbo Code
  • OFDM
  • Abstract This thesis implements the HomePlug AV power line communication system to reduce the probability of decoding errors caused by noise interference during transmission. The architecture of HomePlug AV system includes Scramble, Turbo Code, Interleaver, QAM, FFT, Preamble, etc. Turbo Code is used to perform error correction and the code rate is 1/2. Log-Max Posterior Probability (Log-MAP) is used to decode the Turbo Code. QAM-1024 is applied to the modulated subcarrier. Finally, the fast Fourier transform (FFT) generates the transmitted data to the power line. The Preamble is used as transmitting synchronous signals. The timing recover algorithm will detect whether there is an incoming packet.
    The HomePlug AV system uses the Chip Implementation Center TN90GUTM process to implement the design. The area of transmission part and receiving part is 833,142 μm2 and 1,625,788 μm2. The maximum data transfer rate is 139.46 Mbps which can satisfy the High-quality digital home audio system. The circuit architecture has passed the Chip Implementation Center Cell-Base Design Flow Verification.
    Advisory Committee
  • Shiann-Rong Kuang - chair
  • Xin-Yu Shih - co-chair
  • Ko-Chi Kuo - advisor
  • Files
  • etd-0814117-182647.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2017-09-14

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