Title page for etd-0814117-172820


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URN etd-0814117-172820
Author Hung-Yen Chen
Author's Email Address No Public.
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Department Computer Science and Engineering
Year 2017
Semester 1
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability
Date of Defense 2017-09-14
Page Count 67
Keyword
  • Two bits per conversion
  • Non-binary
  • Time-interleaved
  • Binary search
  • SAR ADC
  • Abstract In this thesis, a 10-bit binary search assisted two channel SAR ADC with a two bit per conversion and error tolerance ability operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt TSMC 90nm process and can be used for receiving in front-end chip of wireless communication system.
    The ADC is divided into two stages, the first level using binary search ADC, in order to achieve high-speed. But the comparator will increase the power consumption as the resolution increases, so the first stage is set to resolve 5 bits. The second srage uses a two-channel 7-bit two-bit conversion of SAR ADC. With a two-bit conversion SAR ADC to speed up, coupled with the dual-channel speed multiplication, in theory, it can be as fast as the binary search ADC. So that even with the Two Stage can also achieve high-speed, high-resolution results. The new capacitor array can be used in a two-bit SAR ADC to achieve fault tolerance mechanisms, and can reduce power consumption effectively without external correction circuit
    Advisory Committee
  • Shiann-Rong Kuang - chair
  • Xin-Yu Shih - co-chair
  • Ko-Chi Kuo - advisor
  • Files
  • etd-0814117-172820.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2017-09-14

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