||The proposed PLL in this thesis is implemented in TSMC 90nm 1P9M RF technology with a 1V supply voltage. This thesis presents a wide tuning and fast locking CMOS integer-N frequency synthesizer. The synthesizer is mainly used for IEEE 802.11ac unlicensed band of Wi-Fi (Wireless Fidelity). It provides one ration frequency ranged from 4.243GHz to 5.202GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer contains a Phase / Frequency Detector, a Low Pass Filter , Comparator, Controllable Operational Transconductance Amplifier, a Charge Pump, a Voltage Control Oscillator, Bootstrapped Switch, Non-overlapping Circuit, Up/Down Counter, and a Pulse-Swallow Divider. |
In order to speed up the lock time, the synthesizer increased the value of gm and the current injection into the LPF by comparing the V_ctrl and change the digital control code of C-OTA.
The simulation result of the synthesizer is shown that the power dissipation is 9.48mW, the output frequency is 4.243GHz~5.202GHz, the lock time is 7.2μs.