Title page for etd-0811117-172407


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URN etd-0811117-172407
Author Jia-hao Chang
Author's Email Address No Public.
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Department Computer Science and Engineering
Year 2016
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Design of Tessellation Unit for 3D Graphic Processor
Date of Defense 2017-07-18
Page Count 70
Keyword
  • tessellation
  • tessellation primitive generation
  • OpenGL 4.x
  • tessellation unit
  • primitive assembly unit
  • Abstract Tessellation shader is one of the advanced graphics rendering functions supported in state-of-the-art graphics standard applications programming interfaces such as OpenGL 4.x and DirextX 11. It provides the programming capability to divide the patches of vertex data into smaller primitives. The tessellation procedure in the graphics pipeline can be divided into three stages: tessellation control shader(TCS), tessellation primitive generation(TPG) and tessellation evaluation shader(TES). This thesis proposes an efficient design of tessellation unit to realize the fixed functions of TPG and the primitive assembly unit(PAU) that can assemble the vertices generated by tessellation into a bunch of triangles. TPG is realized by two-stage pipeline, which includes a setup stage to calculate the vertices of new concentric inner triangles and the edge’s subdivision vector followed by the other stage to serially generate the vertices on the triangle’s edges based on the vectors obtained from the preceding stage. To avoid the expensive divider unit, the required division operation is substituted by multiplying the pre-computed reciprocal factor stored in on-chip look-up tables. One of the salient features of our proposed TPG implementation is to reduce the number of addition/subtraction operations required for generating inner triangles by two thirds by exploring the feature that the sum of three vertices of all concentric inner triangles will be the same. The entire TPG unit only requires two pairs of adders and one pair of multipliers. Its overall gate count is about 25K, and it can run up to 166.7 MHz under 90nm technology. The PAU proposed in this thesis will assemble triangles by dividing the regions of two successive concentric inner triangles into six groups of triangle fans.
    Advisory Committee
  • Chuen-Yau Chen - chair
  • Shen-Fu Hsiao - co-chair
  • Shiann-Rong Kuang - co-chair
  • Yun-Nan Chang - advisor
  • Files
  • etd-0811117-172407.pdf
  • Indicate in-campus at 3 year and off-campus access at 3 year.
    Date of Submission 2017-09-11

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