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URN	etd-0811111-035510
Author	Tsung-Chen Lin
Author's Email Address	No Public.
Statistics	This thesis had been viewed 5576 times. Download 559 times.
Department	Computer Science and Engineering
Year	2010
Semester	2
Degree	Master
Type of Document
Language	zh-TW.Big5 Chinese
Title	Design and Verification of ARM10 ICE Co-Processor
Date of Defense	2011-07-20
Page Count	108
Keyword	Coprocessor Embedded in circuit emulator (EICE) Real-time system debug Microprocessor Static Debug
Abstract	Embedded in circuit emulator (EICE) is the most common and widely used debugging techniques for microprocessors. Because the ICE is capable to provide diverse debugging and testing mechanisms, such as: single-step debugging, breakpoints setting and detection, monitoring, and modification of internal resources. However, the shortcoming of the conventional embedded in circuit emulator (EICE) is that the operation of the processor has to be suspended during debugging, which is categorized as static debugging (Static Debug) and is infeasible for real-time debugging. Therefore, this paper proposes a design alternative to support the real-time system debugging without suspending the microprocessor via the debug hardware Coprocessor14 (the Debug Coprocessor). In this paper, the embedded in circuit emulator is combined with Coprocessor 14 to provide both the static debugging and Run-time system debugging. After incorporating CP14 with the debugging mechanism, the control of the debug hardware is no longer limited to use the IEEE 1149.1 test port during debugging. On the other hand, the set of debugging constraints and the observation of the internal state of the microprocessor can be achieved by inserting the Coprocessor instruction at the program level.
Advisory Committee	none - chair none - co-chair none - co-chair Ing-Jer Huang - advisor
Files	etd-0811111-035510.pdf Indicate in-campus at 2 year and off-campus access at 5 year.
Date of Submission	2011-08-11

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