Title page for etd-0805111-101326


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URN etd-0805111-101326
Author Kuan-Yu Lu
Author's Email Address No Public.
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Department Electrical Engineering
Year 2010
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title A Novel High Integration-Density CMOS Inverter with Unique Shared Contact
Date of Defense 2011-07-15
Page Count 127
Keyword
  • TFET
  • JL MOSFET
  • UTB
  • SOI
  • CMOS
  • Gated N-I-P transistor
  • Abstract A novel CMOS inverter has been proposed. We utilize gated N-I-P transistor to
    replace the conventional PMOSFET for solving the problem of width compensation.
    Also, we carefully investigate and analyze the non-conventional CMOS characteristics
    with NTFET and/or UTB JL MOSFET as driver and gated N-I-P transistor as a load.
    According to the results, our proposed novel CMOS inverter has correct logic behavior
    and its delay time is reduced about 87.2 % when compared with the CTFET. Also, our
    proposed CMOS still can get a 43.2 % reduction in delay time when compared with JL
    CMOS. In addition, because of the N-type output drain node and the SOI structure, our
    proposed CMOS does not need any physical isolation technique, thereby improving the
    packing density. Our proposed CMOS indeed obtain a 54.1 % reduction of the total area
    compared with the conventional CMOS. Our proposed CMOS also can achieve a 40.1
    % reduction in the total area when compared with the SOI-based CMOS. More
    importantly, due to the reduced process steps, the cost reduction can be achieved. We
    therefore believe that a high packing density novel CMOS inverter with reduced process
    steps can become one of the contenders for future CMOS scaling.
    Advisory Committee
  • Chee-Wee Liu - chair
  • Chun-Hsing Shih - co-chair
  • Feng-Der Chin (Albert Chin) - co-chair
  • Wen-Kuan Yeh - co-chair
  • Jyi-Tsong Lin - advisor
  • Files
  • etd-0805111-101326.pdf
  • Indicate in-campus at 99 year and off-campus access at 99 year.
    Date of Submission 2011-08-05

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