Title page for etd-0804114-111344


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URN etd-0804114-111344
Author Ching-Hua Huang
Author's Email Address No Public.
Statistics This thesis had been viewed 5590 times. Download 352 times.
Department Computer Science and Engineering
Year 2014
Semester 1
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC
Date of Defense 2014-08-22
Page Count 123
Keyword
  • Chip Tape-out
  • Logic Synthesis
  • Syetem-on-Chip
  • Three-dimensional Graphics
  • Layout
  • Abstract In recent years, the popularity of handheld smart devices.In order to the demand of consumer and rapid progress of the technological process; Although the design is becoming complex, but the area is still delicate and thin.Today‚Äôs circuit design, its level have been SoC which consist of more than millions logic gates, so the Electronic Design Automation tools has a indispensable role in the design and verification flow.
    Due to the National Science Program, "3D graphics acceleration system" had to chip tape-out. In the front-end process, hardware through the Hardware Description Language to design the sub module-Silicon Intellectual Property; software was developing the Applition Interface and Compiler. Finally, we integrated the ARM7-like CPU and AMBA which were proposed from our laboratory into a system. Since the system integration was a huge task need to considering more, increasing the complexity and performance of verification. Therefore, it was achieved rapid verification by the FPGA Emulation and SystemC, and it's much easier to meet the constraint of time to market.
    Unlike the Front-End process, Back-End processes more emphasis on the impact of process technology and the use of electronic design automation tools to assist in the development of validation. This paper mainly discusses the problems faced by the segment of the process, and how to make the chip in the design process can still maintain a certain degree of stability and effectiveness, and finally through the Chip Implementation Center (CIC) and Taiwan Semiconductor Manufatring Company (TSMC) signing downline commission to achieve the target wafer. In August 2011 and February 2014 reached two SoC chip off the assembly line, respectively 3DG ES1.0 SoC and 3DG ES2.0 SoC.
    In this Research, the goal is pass the back-end implementation and verification process. The difficulties and challenges encountered in the process will be detailed in this thesis, this experience will give follow-up over who can make more success in the real chip.
    Advisory Committee
  • Chung-Ho Chen - chair
  • Da-Wei Chang - co-chair
  • Yun-Nan Chang - co-chair
  • Chung-Fu Kao - co-chair
  • Ing-Jer Huang - advisor
  • Files
  • etd-0804114-111344.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2014-09-04

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