Title page for etd-0801111-105514


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URN etd-0801111-105514
Author Kee-khuan Yu
Author's Email Address No Public.
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Department Computer Science and Engineering
Year 2010
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Multi-Mode Floating-Point Multiply-Add Fused Unit for Low-Power Applications
Date of Defense 2011-07-26
Page Count 61
Keyword
  • iterative multiplication
  • low power
  • truncated addition
  • multi-mode floating point multiply-add-fused
  • Abstract In digital signal processing and multimedia applications, floating-point(FP) multiplication and addition are the most commonly used operations. In addition, FP multiplication operations are frequently followed by the FP addition operations. Therefore, in order to achieve high performance and low cost, multiplication and addition are usually combined into a single unit, known as the FP Multiply-Add Fused (MAF). On the other hand, the mobile devices nowadays are rapidly developing. For this kind of devices, performance and power sustainability have to become the major trend in the research area. As a result, the mechanisms to reduce energy consumption become more important. Therefore, we propose a multi-mode FP MAF based on the concept of iterative multiplication and truncated addition, to achieve different operating modes with different errors. This MAF, with a total of seven modes, includes three modes for the FP multiply-accumulate operations, two modes for single FP multiplication operation and single FP addition operation, respectively. FP multiply-accumulate operations provide three modes to user, and this three modes have 0%, 0.328% and 1.107% of error. The 0% error is the same with the standard IEEE754 single-precision FP Multiply-Add Fused operations. For FP multiplication and FP addition operations, the proposed MAF allows users to choose two kinds of error modes, which are 0%, 0.328% error for FP multiplication and 0%, 0.781% error for FP addition. The 0% error is the same with the standard IEEE754 single-precision floating-point operations.
    When compared with the standard IEEE754 single-precision FP MAF, the proposed multi-mode FP MAF architecture has 4.5% less area and increase about 22% delay to achieve the effect of multi-mode.
    To demonstrate the power efficiency of proposed FP MAF, it is used to perform the operations of FP MAF, FP multiplication, and FP addition in the application of RGB to YUV format conversion. Experimental results show that, the proposed multi-mode FP MAF can significantly reduce power consumption when the modes with error are adopted.
    Advisory Committee
  • Shen-Fu Hsiao - chair
  • Yun-Nan Chang - co-chair
  • Ko-Chi Kuo - co-chair
  • Ming-Chih Chen - co-chair
  • Shiann-Rong Kuang - advisor
  • Files
  • etd-0801111-105514.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2011-08-01

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