Title page for etd-0731116-150758


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URN etd-0731116-150758
Author Jyun-sheng Yang
Author's Email Address No Public.
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Department Computer Science and Engineering
Year 2016
Semester 1
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Design and Implementation of Multi-Port Shared Cache in Multi-core Systems
Date of Defense 2016-08-30
Page Count 76
Keyword
  • multi-port shared cache memory
  • multi-port shared cache memory generator
  • multi-core system
  • Abstract Multi-port shared cache memory plays an important role in multi-core systems. Although single/dual-port SRAM can be realized using commercial standard cell library, multi-port shared cache in systems with more than two cores often requires more than two read/write operations simultaneously, making it impossible to implement such a multi-port cache directly from memory generators supported in most standard cell library. In this thesis, we present a multi-port shared cache memory and adopt the CAM-tag design in the tag array because CAM cells include store unit and compare unit. 8T SRAM cell circuit is used to implement the data array in the cache because it enhances the read and write ability by using two-end write, one-end isolated read. In the thesis, we also develop a generator for the multi-port shared cache using C language program. This generator includes a user interface that allows the user to change design parameters (tag, index, block offset, direct mapping, set-associative) and generate the output layout, verilog code and spice netlist file. Finally we compare the area and timing of multi-port cache for different design styles in various sizes.
    Advisory Committee
  • Tso-Bing Juang - chair
  • Yun-Nan Chang - co-chair
  • Jih-ching Chiu - co-chair
  • Kun-Chih Chen - co-chair
  • Shen-Fu Hsiao - advisor
  • Files
  • etd-0731116-150758.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2016-08-31

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