Title page for etd-0729118-154714


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URN etd-0729118-154714
Author Pei-Hsuan Wu
Author's Email Address No Public.
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Department Computer Science and Engineering
Year 2018
Semester 1
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Architecture Design and Implementation of Deep Neural Network Hardware Accelerators
Date of Defense 2018-08-20
Page Count 89
Keyword
  • CNN hardware accelerator
  • deep neural network (DNN)
  • convolutional neural network (CNN)
  • machine learning
  • Abstract Deep Neural Networks (DNN) widely used in computer vision applications have superior performance in image classification and object detection. However, the huge amount of data movement and computation complexity are two challenges if DNN is used in embedded systems where real-time processing and power consumption are two major design considerations. Hardware DNN accelerators are usually designed using FPGA or ASIC. In this proposal, we develop a memory access method and design a DNN hardware accelerator with fewer memory access and lower power consumption. Using mixed input/output/reuse method, we design a DNN hardware accelerator with 32 processing elements (PEs) that accelerates the computation of VGG16 convolutional layers. The accelerator can achieve a maximum frequency of 515MHz with internal SRAM size of 280 KB using TSMC 40nm process technology. The peak performance of the accelerator is 139 GOP/s, which has better computation speed and power compared to Eyeriss [21].
    Advisory Committee
  • Chung-Ho Chen - chair
  • Yun-Nan Chang - co-chair
  • Chia-Ping Chen - co-chair
  • Ming-Chih Chen - co-chair
  • Shen-Fu Hsiao - advisor
  • Files
  • etd-0729118-154714.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2018-09-03

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