|Author's Email Address
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||Computer Science and Engineering|
|Type of Document
||A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor|
|Date of Defense
Analog to Digital Converter
Successive Approximation Register
||In this thesis, a 10-bit, 10 MS/s dual-mode analog-to-digital converter with a 1.8 V supply voltage is implemented by using the TSMC 0.18m process technology. This circuit primary is implemented for the CMOS Image Sensor.|
In the circuit design, the input source of the analog-to-digital converter is determined by the output of the correlated double sampling or programmable gain amplifier, and both inputs are already sampled. Hence, it is different from the other analog digital converters. The sample and hold circuits can be not required in this cirucit. In combing with the fine step SAR and the coarse step single-slope modes, the edge images can be generated to adjust the sharpness of the image. By using 7 cycles in the capacitance switchig, the 10-bit conversion can effectively reduce the power consumption and increase the conversion efficiency. Because the input has two different signals to be chosen, this circuit also provides two modes of high resolution and low resolution. In the low resolution mode, the shortend and unused circuits also can reduce the power consumption.
In this thesis, a 10-bit, 10 MS/s analog-to-digital converter with a 1.8 V supply voltage is implemented by using the TSMC 0.18 m process technology. The INL and DNL need to be less than 1 and the power consumption should be less than 3mW.
||Shiann-Rong Kuang - chair|
Xin-Yu Shih - co-chair
Ko-Chi Kuo - advisor
Indicate in-campus at 5 year and off-campus access at 5 year.|
|Date of Submission