| URN |
etd-0728114-115349 |
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| Author |
Shao-Chieh Hou |
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| Author's Email Address |
No Public. |
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| Statistics |
This thesis had been viewed 5573 times. Download 409 times. |
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| Department |
Computer Science and Engineering |
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| Year |
2013 |
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| Semester |
2 |
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| Degree |
Master |
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| Type of Document |
|
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| Language |
English |
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| Title |
Integration of C Source Level Debugging and HW Tracing and Monitoring |
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| Date of Defense |
2014-07-18 |
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| Page Count |
95 |
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| Keyword |
Debugger
JTAG
Co-Debugging
|
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| Abstract |
With the increasing of manufacture and software design technology, embedded system now
become more and more complex, time-to-market also become more short. For integrated a
system-on-chip (SoC), how to debug the errors while integrate become a important problem.
This thesis proposed a method that integrate both software and hardware debugging. To catch
the HW transaction information by using the embedded in-circuit emulator(EICE) in micropro-
cessors and the proposed wrapper-base in-circuit emulator(WBICE) between IP and wrapper.
Abstract the signals trace from HW and display both SW and HW debug information in the
same degubber. Reference to SW debug actions and command to design HW debug actions
and commands, make user can control and debug both SW and HW in the same interface. Let
HW debugging like SW debugging. Reduce the integration time and time-to-market. |
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| Advisory Committee |
Kuen-Jong Lee - chair
Qi-Feng Wu - co-chair
Steve Haga - co-chair
Fu-Ching Yang - co-chair
Ren-Song Tsay - co-chair
Ing-Jer Huang - advisor
|
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| Files |
Indicate in-campus at 3 year and off-campus access at 3 year. |
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| Date of Submission |
2014-08-28 |
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