Title page for etd-0728114-115349


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URN etd-0728114-115349
Author Shao-Chieh Hou
Author's Email Address No Public.
Statistics This thesis had been viewed 5573 times. Download 409 times.
Department Computer Science and Engineering
Year 2013
Semester 2
Degree Master
Type of Document
Language English
Title Integration of C Source Level Debugging and HW Tracing and Monitoring
Date of Defense 2014-07-18
Page Count 95
Keyword
  • Debugger
  • JTAG
  • Co-Debugging
  • Abstract With the increasing of manufacture and software design technology, embedded system now
    become more and more complex, time-to-market also become more short. For integrated a
    system-on-chip (SoC), how to debug the errors while integrate become a important problem.
    This thesis proposed a method that integrate both software and hardware debugging. To catch
    the HW transaction information by using the embedded in-circuit emulator(EICE) in micropro-
    cessors and the proposed wrapper-base in-circuit emulator(WBICE) between IP and wrapper.
    Abstract the signals trace from HW and display both SW and HW debug information in the
    same degubber. Reference to SW debug actions and command to design HW debug actions
    and commands, make user can control and debug both SW and HW in the same interface. Let
    HW debugging like SW debugging. Reduce the integration time and time-to-market.
    Advisory Committee
  • Kuen-Jong Lee - chair
  • Qi-Feng Wu - co-chair
  • Steve Haga - co-chair
  • Fu-Ching Yang - co-chair
  • Ren-Song Tsay - co-chair
  • Ing-Jer Huang - advisor
  • Files
  • etd-0728114-115349.pdf
  • Indicate in-campus at 3 year and off-campus access at 3 year.
    Date of Submission 2014-08-28

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