Title page for etd-0726114-101438


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URN etd-0726114-101438
Author CHUN-TO HSU
Author's Email Address No Public.
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Department Computer Science and Engineering
Year 2013
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM
Date of Defense 2014-07-29
Page Count 78
Keyword
  • RTL Compiler
  • ROM generator
  • Programmable Logic Array (PLA)
  • ROM Compiler
  • Abstract Read-only memory (ROM) plays an important role In modern System-on-Chip (SoC) designs. Due to the regularity of ROM structure, ROM components are usually generated through automatic ROM compiler/generator. For example, ARM TSMC cell library provides ROM compiler to automatic synthesize ROM of arbitrary size. In general, there are two different types of ROM implementations, conventional ROM structure or programmable logic array (PLA). For the implementation with the conventional ROM structure, we adopt the dynamic NAND-based circuit design with multi-level decoder to reduce the area cost. Regarding PLA-based implementation, the dynamic NOR-NOR structure is used where the logic optimization of product terms is performed using the Espresso logic minimization tool.We develop automatic ROM generators for both ROM structures and make comparison with those obtained from ARM ROM compiler and those directly synthesized from combination logic using Synopsys RTL (Register Transfer Level) Design Compiler. Based on the extensive comparisons of area, delay and power for ROM in various sizes, we make several interesting observations, and try to improve our ROM generators in order to make them more competitive for synthesis of large ROM size.
    Advisory Committee
  • Chuen-Yau Chen - chair
  • Jih-ching Chiu - co-chair
  • Shiann-Rong Kuang - co-chair
  • Ming-Chin Chen - co-chair
  • Shen-Fu Hsiao. - advisor
  • Files
  • etd-0726114-101438.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2014-08-26

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