Title page for etd-0726111-142933


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URN etd-0726111-142933
Author Chi-Guang Lin
Author's Email Address newq3731@hotmail.com
Statistics This thesis had been viewed 5351 times. Download 3266 times.
Department Computer Science and Engineering
Year 2010
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Bus Interface Design Between Different Clock Domains and Its Application to OpenGL-ES 2.0 3D Graphics Systems
Date of Defense 2011-01-26
Page Count 89
Keyword
  • vertex shader
  • Open Core Protocol
  • OpenGL ES 2.0
  • AHB
  • asynchronous bus interface
  • Abstract Asynchronous bus interface units to AMBA AHB are designed so that an OpenGL ES 2.0 vertex shader can communicate with other hardware units via AHB bus under different working frequencies. The first design is to directly implement an asynchronous AHB wrapper for the vertex shader. The other two designs are based on Open Core Protocol (OCP) to allow for more flexibility. The hardware intellectual property (IP), vertex shader in this thesis, to OCP asynchronous unit is designed so that the IP can be developed independently with different bus protocols as long as the OCP-to-bus interface is provided for a particular bus protocol. With the help of asynchronous IP-to-OCP and OCP-to-AHB interface units, the vertex shader IP can operate at different frequencies from the AHB bus. Furthermore, the same vertex shader (VS) can be connected to other bus protocol (such as AXI) of different frequencies if the OCP-to-AXI interface is provided because the the asynchronous VS-to-OCP have been designed in this thesis.
    Advisory Committee
  • Jih-ching Chiu - chair
  • Ming-Chih Chen - co-chair
  • Chuen-Yau Chen - co-chair
  • Ming-Chih Chen - co-chair
  • Shen-Fu Hsiao - advisor
  • Files
  • etd-0726111-142933.pdf
  • indicate in-campus access immediately and off_campus access in a year
    Date of Submission 2011-07-26

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