||In this thesis, a 10-bit, 80 MS/s analog-to-digital converter with a 1 V supply voltage is implemented by using the TSMC 90nm process technology. This circuit can be used in the applications for the wireless communications.|
In the circuit design, in order to achieve a higher operation speed and better conversion precision, a 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction architecture is proposed by adapting the dynamic comparator techniques to reduce static power consumption. In order to achieve the high-speed operation requirement, the non-binary capacitor array switching and digital correction methods are adapted and it can increase the fault tolerant capability by comparing capacitance before they are stabled. On the other hand, the symmetrical bootstrapping switch is implemented to control the front end sampling switch to improve the conversion speed of the proposed analog-to-digital converter, and thus achieve lowering the non-linearity effects on the sample and hold circuit due to the lowered voltage operation.
This paper presents 80 MS/s and 10 bit analog-to-digital converter, which DNL is + 0.997-1 LSB, INL is + 1.351 / -1.464 LSB, SFDR and SNDR at the Nyquist rate are 65.453 dB and 56.327 dB, ENOB is 9.064 bit, power consumption is 2.19 mW, finally FOM of 51 fJ / conv.-step.
Keywords: Analog to Digital Converter、Successive Approximation Register、2b/Cycle、digital error correction、non-binary digital error correction