Title page for etd-0723115-165419


[Back to Results | New Search]

URN etd-0723115-165419
Author Yi-Lin Ye
Author's Email Address No Public.
Statistics This thesis had been viewed 5351 times. Download 0 times.
Department Electrical Engineering
Year 2015
Semester 1
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Design Instruction Analyzer in the Hyper-scalar Architecture
Date of Defense 2015-08-17
Page Count 69
Keyword
  • ILP
  • virtual shared register file
  • hyper-scalar
  • instruction analyzer
  • Abstract When the Hyper-scalar microprocessor system architecture performs the same thread, it cause the delay of data transmit and reduce the performance due to the dependence between instructions which result in a frequently data interact between cores in the Virtual Shared Register File (VSRF) transmission. Therefore, we propose Instruction Analyzer to solve the problem of dependence between instructions. When an instruction depends on another instruction, both of the instructions would be issued to the same core as far as possible. In order to improve the whole architecture performance, the number of data interaction between cores will be substantially reduced in the VSRF
    Before being issued to the appropriate core, instructions must be analyzed according to dependence by Instruction Analyzer. There are four stages in the whole procedure. First, Instruction Fetch: In order to improve the parallelism of instruction level, it will cooperate with Branch Predictor and fetch four instructions at the same time in this stage. Second, Register Tag: Operand tags and conditional tags will be generated according to the dependence between instructions. Register destination tag will be determined according to the most appropriate result of the operand tags and the conditional tags. Third, Dependence Analyzer: Core tags will be generated according to the register tags and decide the core which the instruction will be issued to. Fourth, Dispatch: Cycle tags will be generated according to the core tags and decide when the instruction must be issued. The result of cycle tags will be recorded in the Defer Table. This stage is the most important part of Instruction Analyzer. There must be a PC Detector that judge whether Instruction Analyzer fetch the correct instructions. When the Instruction Analyzer fetches wrong instructions, a compensation mechanism would direct the PC to correct the instruction address.
    We verify whether this architecture could efficiently issue instructions by testing programs and reduce the number of data interaction between cores in the VSRF. According to the simulation result, the number of data interaction between cores in the VSRF reduces to half after Instruction Analyzer is applied. Therefore, we implement Instruction Analyzer that not only raise the core usage but also reduce the number of data interaction between cores in the VSRF.
    Advisory Committee
  • Shiann-Rong Kuang - chair
  • Zi-Tsan Chou - co-chair
  • Tong-Yu Hsieh - co-chair
  • Jih-ching Chiu - advisor
  • Files
  • etd-0723115-165419.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2015-08-24

    [Back to Results | New Search]


    Browse | Search All Available ETDs

    If you have more questions or technical problems, please contact eThesys