| URN |
etd-0722117-115932 |
|---|
| Author |
Bo-chien Hsiao |
|---|
| Author's Email Address |
moritz@garfield.cse.nsysu.edu.tw |
|---|
| Statistics |
This thesis had been viewed 5339 times. Download 449 times. |
|---|
| Department |
Computer Science and Engineering |
|---|
| Year |
2016 |
|---|
| Semester |
2 |
|---|
| Degree |
Master |
|---|
| Type of Document |
|
|---|
| Language |
zh-TW.Big5 Chinese |
|---|
| Title |
FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming |
|---|
| Date of Defense |
2017-07-25 |
|---|
| Page Count |
61 |
|---|
| Keyword |
image rectification
dynamic programming
depth map
stereo matching
FPGA
stereo vision
|
|---|
| Abstract |
Stereo vision is widely used in many computer vision applications including games, autonomous driving, object recognition, etc. Depth is the key information in stereo vision. In general, depth map is generated by stereo matching computation of two input images captured by cameras at different view angles. In this thesis, we use FPGA SoC platforms to realize a real-time dynamic programming-based stereo matching algorithm where the left and right input images are captured real-time and the computed depth maps are shown on screen. Image rectifications are also considered during the implementations. We study and analyze various hardware-software co-design options and improve the performance using different hardware platform environments. |
|---|
| Advisory Committee |
Chung-Ho Chen - chair
Shiann-Rong Kuang - co-chair
Kun-Chih Chen - co-chair
Shen-Fu Hsiao - advisor
|
|---|
| Files |
indicate access worldwide |
|---|
| Date of Submission |
2017-08-22 |
|---|
