Title page for etd-0717117-011637


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URN etd-0717117-011637
Author Yu-xiang Peng
Author's Email Address No Public.
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Department Electrical Engineering
Year 2016
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Development of a Miniaturized Suspended Transformer-based Power Divider with High-k Dielectric Capacitors
Date of Defense 2017-07-27
Page Count 114
Keyword
  • NEMS
  • surface micromachining
  • High-k dielectric
  • copper electroplating fabrication processes
  • suspended structure
  • power divider
  • Abstract Since the Internet of Things (IoT) and Internet of Vehicle (IoV) markets are increasing rapidly, the wireless communication system with higher data rate, information accuracy and farther transmission distance are developed for matching the requirements of the multi-input multi-output (MIMO) techniques. However, there are similar passive and active devices with the same functions consume extra area in the MIMO receiver system. In order to improve the disadvantage, this thesis designed and developed a multiplex power divider replaced two traditional power dividers utilizing the surface micromachining process, and diminish the dimensions of divider for the needs of wireless communications network products.
    To realize the power divider with four-phase outputs, low transmission losses and compact size characteristics, the main fabrication processes in this thesis including: (i) Employ two central tapped power divider to reduce the chip size; (ii) Utilize suspended structure to reduce the insertion loss caused by parasitic capacitance between device and substrate; (iii) High dielectric constant material (zirconium oxide) used as the dielectric layer to significantly reduce dimension. This power divider constructed of bottom electrode, supporting posts and top electrode. The main fabrication processes including six thin-film depositions, three copper electroplating, five graphic definitions of photolithography and four etching processes.
    Compared with our previous research (Chia-Lung Song, senior, 2016). The chip size is significantly reduced from 2900 μm (L) × 2800 μm (W) × 21 μm (H) to 1290 μm (L) × 1060 μm (W) × 24.15 μm (H), the reduction range is about 593%. The multiplex power divider with 2.4 GHz operating frequency and measured from 10 MHz to 8.0 GHz by network analyzer. There were two generations of the power divider in this thesis. The initial generation with double-layer capacitance showed the four output insertion losses are -71.10, -57.25, -50.83 and -71.33 dB, and -10.89, -12.27, -8.98 and -15.98 dB in the subsequent generation with single-layer capacitance, all the output insertion loss characteristics improved above than 78%. Moreover, the input return losses enhanced from -0.34 and -0.32 dB to -1.34 and -1.17 dB, which improved 294% with early. The output return losses demonstrate -0.82, -0.84, -0.87 and -0.69 dB in the previous generation, and -1.51, -2.09, -7.25 and -2.18 dB in the following generation, which enhanced more than 84%. Compare with the standard phase difference (180°), the initial generation exhibited 87.99° and 61.42°, whereas 9.93° and 0.50° in the subsequent generation.
    Advisory Committee
  • Yu-Cheng Lin - chair
  • Feng-Renn Juang - co-chair
  • Cheng-Yu Ma - co-chair
  • I-Yu Huang - advisor
  • Files
  • etd-0717117-011637.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2017-08-25

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