Title page for etd-0716117-154234


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URN etd-0716117-154234
Author Ting-pi Hsu
Author's Email Address No Public.
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Department Electrical Engineering
Year 2016
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density
Date of Defense 2017-07-27
Page Count 155
Keyword
  • CMOS
  • punch through transistor
  • junctionless transistor
  • high integration density
  • low power dissipation
  • vertical channel
  • Abstract In this thesis, we propose a vertical channel non-classical CMOS (VNCCMOS) with low power dissipation and high integration density. Junctionless transistor and punch through transistor replaced conventional NMOS and PMOS respectively in our structure for use in low power supply systems. The operating mechanisms of respective junctionless transistor (JLMOS) and punch through transistor (PTMOS) are further analyzed in depth. The threshold voltage (VTH) and the flat-band voltage (VFB) are used in JLMOS and PTMOS respectively. 
    This VNCCMOS circuit achieves subthreshold swing = 66 mV/dec and 67 mV/dec of Q1 junctionless transistor and Q2 punch through transistor respectively. Both transistors’s ION/IOFF can be close to 104 at power supply VD = 0.3 V. The VNCCMOS obtain low power dissipation (PD) = 2.01 nW. The power delay product of VNCCMOS is better than conventional planar CMOS (CMOS) and planar non-classical CMOS (NCCMOS). The VNCCMOS with vertical channel is good for scaling down. Our structure can reduced the layout area by 56.5 % compared with conventional CMOS inverter. The VNCCMOS reaches low power dissipation and high integration density.
    Advisory Committee
  • Chee-Wee Liu - chair
  • Kow-Ming Chang - co-chair
  • Jinn-Shyan Wang - co-chair
  • Feng-Der Chin - co-chair
  • Jyi-Tsong Lin - advisor
  • Files
  • etd-0716117-154234.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2017-08-22

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