Title page for etd-0716114-030526


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URN etd-0716114-030526
Author Bo-ting Lin
Author's Email Address No Public.
Statistics This thesis had been viewed 5384 times. Download 14 times.
Department Computer Science and Engineering
Year 2013
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Low-power Multi-precision Functional Unit Generator for 3-D Graphics Application
Date of Defense 2014-07-24
Page Count 88
Keyword
  • multi-mode floating point multiply-add-fused
  • low power
  • generator
  • multi-precision function interpolator
  • Abstract A multi-precision function interpolator generator and a multi-precision MAF generator, which is compliant in with the IEEE-754 single precision floating point standard, is proposed in this paper. Users can generate different hardware architecture with multi-precision according to their requirement. Function interpolator provides logarithms, exponentials, reciprocal and square root reciprocal operations. On the other hand, MAF provides multiplication, addition, and multiply-accumulation, and each operation can be calculated in different precisions. The hardware architecture is designed with full pipeline in order to comply with hardware architectures of general digital signal processors (DSPs) and graphic processors (GPUs).
    This function interpolator is designed based on the look-up table method. It can get the approximation value of target function through the calculation of quadratic polynomial. MAF combines floating-point multiplication and accumulation into one single unit to execute multiply-accumulation operation. When executing multiplication, it will align the decimal point in addition process at the same time.
    Multi-precision function interpolator and MAF not only have the highest precision mode, they also can execute low precision modes. In low precision mode, system will shut down partial product bits hardware components that are not being used. Users can choose different types of the precision levels needed, and generators will automatically create the hardware architectures and Verilog codes. Different hardware for achieving different precision modes would not conflict with each other, and all operations will meet the precision requirement.
    When generating the hardware architecture without the highest precision level, the generator will add the clock gating cells and latches for different precision modes. When producing these approximation values, the switches added will shut down the unnecessary components in order to reduce the power consumption. Executing one of the four functions in the function interpolator will only search for its own calculation’s table to find the coefficients of quadratic polynomial. Therefore, the latch can be added as switches to reduce dynamic power consumption of tables for the other three functions. Thus, even when executing in the highest precision level, the power consumption can also be reduced. When MAF only performing multiplications, latches are added to shut down parts of the accumulation hardware. On the contrary, when it only performing accumulations, parts of the multiplication hardware are shutdown to reduce the power consumption.
    As mentioned above, the multi-precision function interpolator generator and the multi-precision MAF generator can generate different hardware architectures with different precision modes for different requirement to reduce the power consumption and extend the battery’s lifetime of the device.
    Advisory Committee
  • Pei-Yin Chen - chair
  • Yu-Hung Hsiao - co-chair
  • Ren-Der Chen - co-chair
  • Shiann-Rong Kuang - advisor
  • Files
  • etd-0716114-030526.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2014-08-18

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