Title page for etd-0712113-115821


[Back to Results | New Search]

URN etd-0712113-115821
Author Chang-Teng Chiu
Author's Email Address No Public.
Statistics This thesis had been viewed 5343 times. Download 46 times.
Department Computer Science and Engineering
Year 2012
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title High-performance High-radix Montgomery Modular Multiplier
Date of Defense 2013-07-23
Page Count 67
Keyword
  • RSA Cryptosystems
  • High-performance
  • Modular Multiplier
  • High-radix
  • Montgomery’s Algorithm
  • Abstract In this information age, the internet plays a very important role in our lives. When people send and receive data on the public network, their personal data may be stolen by the other people. In order to ensure that the data remains safe and confidential, the data have to be encrypted before transmission. Therefore, the cryptosystem is important and popular today.
    RSA is the one of widely used public-key cryptosystems. Its principle was established in theory of prime numbers. The RSA operation is a modular exponentiation, which is usually achieved by repeated modular multiplications. It would be difficult to achieve real-time transmission on the internet by running software programs. Hence we will implement RSA cryptosystems with hardware architectures.
    Modular multiplication (A × B mod N) is the key operation in RSA cryptosystems. A famous approach to implement the modular multiplication into hardware architectures is based on the Montgomery modular multiplication algorithm, which replaces the traditional division with a series of addition and shift operations. For security reasons, RSA operand sizes need to be 512 bits or greater. However, a large amount of clock cycles is required to complete a modular multiplication by traditional Montgomery modular multiplication algorithm.
    The thesis presents an improved High-radix Montgomery modular multiplier. It computes multi-bit addition and shift operations in a clock cycle. Therefore, the drawback of great clock cycles is solved. In addition, carry save adders are used to avoid the carry propagation. Experimental results show that the proposed pre-computation and sub-processing design significantly reduce the delays of modular multiplier, leading to higher performance.
    Advisory Committee
  • Shen-Fu Hsiao. - chair
  • Yun-Nan Chang - co-chair
  • Jih-Ching Chiu - co-chair
  • Ko-Chi Kuo - co-chair
  • Shiann-Rong Kuang - advisor
  • Files
  • etd-0712113-115821.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2013-08-15

    [Back to Results | New Search]


    Browse | Search All Available ETDs

    If you have more questions or technical problems, please contact eThesys