||Recently, electronic products combining display panels, memory devices, and portable devices have become more popular for consumers. These electronic products are mostly composed of metal-oxide-semiconductor field effect transistors (MOSFETs). It is due to MOSFETs having the advantage of low cost, low power consumption and the ability to be scaled down easily. However, continuous scaling down of traditional MOSFETs can face problems like, gate leakage, short channel effect…etc. It not only reduces gate control ability but also increases device power consumption. To solve these problems, silicon on insulator, (SOI), high-k/metal gate stack structure, and Fin Field Effect Transistors (FinFETs) have been used. Therefore, in this dissertation, we will focus on n-type MOSFETs and FinFETs devices to investigate electrical characteristics, hot carrier stress (HCS), and positive bias stress (PBS). This dissertation can be roughly divided into two parts based on device structure. One is partially depleted silicon on insulator, (PD-SOI) and the other is FinFETs. |
The PD SOI MOSFETs section is divided into three sections to investigate the physical mechanisms and hot carrier degradation. The first PD SOI section, we investigates the behavior of hot carrier-induced degradation at different temperatures under GB and FB operations, and finds that the degradation under FB is more serious than that under GB operation due to the floating body effect. Fast I–V shows a drain current rise after FB-HCS. This can be attributed to the fact that impact-ionization-generated holes are injected into the floating substrate. Next experience with hot carrier stress degradation with different temperature, and find the degradation under FB operation becomes less significant with increasing temperature. This is due to the lessened ability to retain holes at the source/body PN junction at high temperature and the resultant insignificant FBE. According to this study, hot-carrier-induced degradation under GB operation at different temperatures is dominated by the impact ionization rate, while the degree of degradation under FB operation is dominated by the ability to retain holes at the source/body PN junction.
In the second PD-SOI section, founded and investigated abnormal charge pumping current (ICP) in body-tied partially-depleted silicon-on-insulator n-channel metal-oxide-semiconductor field effect transistors. The ICP second hump region increases with channel length, yet is not affected by channel width in the L-gate structure. Because of a part of the poly gate area near the body contact is covered by a P+ implant, inducing a parasitic channel under the P+ poly gate. This parasitic channel leads to the abnormal Gm and ICP hump, and such mechanism is further verified by different measurement and reliability methods.
In the second PD-SOI section, we investigates the origin of an anomalous enhancement in on-state current under hot carrier stress and temperature dependent hot-carrier-induced degradation in lateral diffused SOI n-MOSFETs. Threshold voltage and subthreshold swing degrade, whereas an abnormal on-state current exhibits a quick rise after HCS due to hole trapping in the resist-protective oxide. Impact ionization simulation shows that low doping concentrations in the drift region causes a severe Kirk effect under HCS and more severe degradation at higher VG. Notably, degradation in the channel contrasts with the simulation result, which suggests another mechanism. Moreover, variable temperature HCS verifies that channel degradation is dominated by temperature.
Finally, in the high-k/metal gate stack FinFETs section, we also investigated electrical characteristics and reliability. The first section in FinFETs, we investigates the mechanism of abnormal body current at the linear region in n-channel high-k/metal gate stack FinFETs. Unlike body current, which is generated by impact ionization at high drain voltages, abnormal body current was found to increase with decreasing drain voltages. Notably, the unusual body leakage only occurs in three-dimensional structure devices. Based on measurements under different operation conditions, the abnormal body current can be attributed to fin surface defect-induced leakage current, and the mechanism is electron tunneling to the fin via the defects, resulting in holes left at the body terminal.
In the second section of FinFETs, we investigate an abnormal transconductance (Gm) enhancement after positive bias stress (PBS) in n-channel HK/MG FinFETs. This abnormal Gm enhancement after PBS is observed only in short channel devices. With the speculation that hole-trapping-induced electron accumulation is the dominant mechanism, PBS with floating source and drain is adopted as an investigative approach. This, together with the electric field simulation, verifies that hole-trapping in the HfO2 and SiN near the gate corner induces electron accumulated at the ends of the channel length. Such a phenomenon results in a shortening of effective channel length and further Gm enhancement