Title page for etd-0707112-015601


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URN etd-0707112-015601
Author Wayne Luo
Author's Email Address No Public.
Statistics This thesis had been viewed 5562 times. Download 0 times.
Department Electrical Engineering
Year 2011
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title 2.45 GHz ZigBee Receiver Frontend and Delta-Sigma ADC with Constant-gm Amplifier for Battery Management Systems
Date of Defense 2012-06-18
Page Count 78
Keyword
  • BMS
  • ZigBee
  • receiver
  • Delta-Sigma ADC
  • constant-gm amplifier
  • Abstract This thesis consists of two topics: A 2.45 GHz ZigBee Receiver Frontend design for home energy-saving systems and a Delta-Sigma ADC with constant-gm amplifier for Battery Management Systems (BMS).
    A 2.45 GHz ZigBee Receiver Frontend for home energy-saving systems is pre-sented in the first part of this thesis. The proposed ZigBee receiver can be used in areas where wireline solutions are hard to be realized. By employing an LNA at the very frontend of the receiver, the gain is simulated to be 17.376 dB at 2.45 GHz. Besides, by using the double-balanced Gilbert mixer with a current bleeding MOS transistor, the NF and the IIP3 of the mixer are only 5.074 dB and -7.234 dB, respectively. To reduce the phase noise of the receiver, a fractional-N frequency synthesizer with a complementary cross-coupled VCO is adopted. The phase noise of the fractional-N frequency synthe-sizer is 137.7 dBc/Hz. The proposed circuit is carried out and measured on silicon using the standard TSMC 0.18 μm CMOS process.
    In the second topic, a Delta-Sigma ADC with constant-gm amplifier is presented. The proposed ADC is particularly designed for the voltage detection circuit in BMS. A constant-gm amplifier is also presented to resolve the nonlinearity of the amplifier de-grading the performance of Delta-Sigma modulator, which is the frontend of the Del-ta-Sigma ADC. With the 4 KHz signal bandwidth, 512 KHz sampling frequency, and 128 oversampling rate, it shows a 85.2 dB SNR, and 12-bit resolution. The backend of the ADC is the decimator, which reduces the sampling frequency compliant with the Nyquist rate rule. The decimator is realized by Verilog code and verified by FPGA. By following the mixed-signal flow, the ADC is realized on a single chip using the standard TSMC 0.25 μm 60V HV CMOS process.
    Advisory Committee
  • Chin-Long Wey - chair
  • Shen-Fu Hsiao - co-chair
  • Jih-ching Chiu - co-chair
  • Chua-Chin Wang - advisor
  • Files
  • etd-0707112-015601.pdf
  • Indicate in-campus at 99 year and off-campus access at 99 year.
    Date of Submission 2012-07-07

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