Title page for etd-0706105-152354


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URN etd-0706105-152354
Author Kai-fang Cheng
Author's Email Address m923010044@student.nsysu.edu.tw
Statistics This thesis had been viewed 5561 times. Download 11291 times.
Department Electrical Engineering
Year 2004
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Design and Modeling of Power Factor Correction Circuits
Date of Defense 2005-06-26
Page Count 102
Keyword
  • PFC
  • PI controller
  • boost converter
  • Abstract This thesis aims to investigate an active power factor correction (PFC) circuit and its mathematical model, in order to develop a reliable and efficient simulation platform. By using the PI controller, we can control the inductor current and the output voltage of the boost converter. Finally, we constructed the circuit and analyzed the results to verify that our mathematical model is valid.
    Advisory Committee
  • I-chih Kao - chair
  • Zai-jun Yu - co-chair
  • Yung-chun Wu - co-chair
  • Chin-ching Huang - co-chair
  • Tzuen-lih Chern - advisor
  • Files
  • etd-0706105-152354.pdf
  • indicate access worldwide
    Date of Submission 2005-07-06

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