Title page for etd-0701109-205501


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URN etd-0701109-205501
Author Yi-cheng Liu
Author's Email Address No Public.
Statistics This thesis had been viewed 5559 times. Download 3910 times.
Department Electrical Engineering
Year 2008
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3×VDD Wide Range Mixed-Voltage-Tolerant I/O Cell
Date of Defense 2009-06-18
Page Count 76
Keyword
  • I/O cell
  • Mixed-Voltage-Tolerant
  • Dynamic Biasing
  • Sub 3×VDD
  • Abstract The thesis is composed of tow topics: a fully bidirectional mixed- voltage-tolerant I/O cell using a new output stage circuit and a sub-3×VDD wide range fully bidirectional mixed-voltage-tolerant I/O cell.
    The first topic discloses a mixed-voltage-tolerant I/O cell implemented using 2P4M 0.35 μm CMOS process, which uses a low static power dynamic gate bias generator providing three different logic voltage levels to the output stage to avoid gate oxide reliability and leakage current. The design also reveals a new output stage circuit, which enhances the output current to resolve the poor driving capability caused by the slow mobility and body effect of the stacked PMOS.
    The second topic shows a sub-3×VDD wide range fully bidirectional mixed-voltage-tolerant I/O cell using 1P6M 0.18 μm CMOS process, which employs a new dynamic gate bias generator and a PAD voltage detector to provide appropriate gate biases. The design includes a new gate tracking circuit and a floating N-well circuit to avoid gate oxide reliability and leakage current, which relaxes the body effect at the output PMOS.
    Advisory Committee
  • Sying-Jyan Wang - chair
  • Shen-Fu Hsiao - co-chair
  • Jih-ching Chiu - co-chair
  • Chua-Chin Wang - advisor
  • Files
  • etd-0701109-205501.pdf
  • indicate in-campus access immediately and off_campus access in a year
    Date of Submission 2009-07-01

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