Title page for etd-0629113-155339


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URN etd-0629113-155339
Author Kai-Yang Hsieh
Author's Email Address wesker760408@hotmail.com
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Department Computer Science and Engineering
Year 2012
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection
Date of Defense 2013-06-07
Page Count 71
Keyword
  • Commercial ATPG Tool
  • False Path
  • Statistical Static Timing Analysis
  • Timing-aware ATPG
  • Small Delay Defect
  • Abstract Small Delay Defect (SDD) is one kind of the signal transition delay faults. It could not be detected via traditional delay testing method because the delay time is too small, however, the-se faults could cause timing failure in the circuit when the accumulation of delay time along the paths is too much.
    Typical SDD testing uses commercial ATPG Tools, generating SDD test patterns to detect. Since the delay time of SDD is too small, SDD exists too much in the circuit. Thus, SDD has to sensitize more paths to generate SDD test patterns during test pattern generation and too much CPU runtime.
    Using commercial ATPG Tools for SDD testing, it has to consider delay information in the circuit by static timing analysis (STA) tools. However, there are false paths in the circuit, which makes delay time calculation much more pessimistic and leads to unnecessary SDDs.
    The thesis proposed the method to detect the false paths during timing analysis to exclude the false paths and redundant faults, and meanwhile to apply statistical static timing analysis (SSTA) to calculate timing instead of STA in order to reduce SDD count and pattern count.
    Advisory Committee
  • Jwu-E Chen - chair
  • Chung-Nan Lee - co-chair
  • Shen-Fu Hsiao. - co-chair
  • ko-chi kuo - co-chair
  • Shu-Min Li - advisor
  • Files
  • etd-0629113-155339.pdf
  • Indicate in-campus at 99 year and off-campus access at 99 year.
    Date of Submission 2013-08-21

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