|Author's Email Address
||This thesis had been viewed 5563 times. Download 2867 times.|
|Type of Document
||A Load-Optimized 500 MHz VCO Design for Phase-Locked Loop and Half-Swing PLA and The Applications for High-Speed Circuit Design|
|Date of Defense
||The first topic of this thesis is a practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop. Besides the low jitter advantage, the design also possesses another feature, i.e., fast locked time.|
The second topic is the half-swing PLA circuit. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes of PLAs to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced and the dynamic power is reduced.
The third topic is a novel design of a the 1.0 GHz pipelining 8-bit CLA based on the architecture we mentioned in the second topic. The operating clock frequency is 1.0 GHz and the output of the addition of two 8-bit binary numbers is done in 2 cycles ( 2.0 ns ).
||Sying-Jyan Wang - chair|
Yau-Hwang Kuo - co-chair
Chau-Chin Wang - advisor
indicate accessible in a year|
|Date of Submission