Title page for etd-0625113-170420


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URN etd-0625113-170420
Author Xue-Da Ko
Author's Email Address No Public.
Statistics This thesis had been viewed 5357 times. Download 190 times.
Department Computer Science and Engineering
Year 2012
Semester 2
Degree Master
Type of Document
Language English
Title Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology
Date of Defense 2013-07-17
Page Count 81
Keyword
  • Static Timing Analysis
  • Level Converter
  • Critical Path
  • Multiple-Supply Voltage
  • Abstract With the improvement of semiconductor manufacturing processes, the power consumption of the integrated circuit(IC) is growing rapidly. Therefore, the power consumption reduction of IC is also becoming an important issue. If we cannot reduce the power consumption effectively such that it will cause the IC overheat and its functional failure. In order to preserving the normal operation and extend the battery life of the chips. Nowadays, the chips are usually saving the power consumption by reducing the supply voltage. However, it will affect the performance of the chips by reducing the supply voltage directly. Under the premise, there is a direct and effective method that it can reduce the power consumption and without affect the performance for designing the IC by the Multiple Supply Voltage architecture (MSV).
    With the narrower line width in the VLSI processes, the processes resolution is smaller than the wavelength of Optical Lithography. Hence, the error control of the fabrication cannot accurate increasingly. Therefore, there are many similar statistical distributions of the errors emerged and present many relevant even in the same manufacturing environment. For the reason that using the Static Timing Analysis to identify the critical path could be inaccurate. In order to overcoming this problem, this thesis proposes a method to design the MSV chips which is using greedy algorithm to make voltage assignment on the IC. Then we use the Statistical Static Timing Analysis for analyzing and verifying the timing of circuit. It can search the Path Sensitivity which exactly equals to the probability of the path that is critical path. We embed the Level Converter that we designed into the combinational circuit by using Cell-Based manner and let some cells applying the appropriate lower supply voltage to substitute the higher supply voltage for achieving the purpose of reducing power consumption.
    Advisory Committee
  • Shiann-Rong Kuang - chair
  • Yun-Nan Chang - co-chair
  • Ko-Chi Kuo - co-chair
  • Hsiao-Chin Chen - co-chair
  • Ko-Chi Kuo - advisor
  • Files
  • etd-0625113-170420.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2013-07-25

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