|Author's Email Address
||This thesis had been viewed 5564 times. Download 54 times.|
||Computer Science and Engineering|
|Type of Document
||A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design|
|Date of Defense
||A high speed and low power Pipelined-SAR ADC is proposed in this thesis. The Flash ADC which is often found in traditional Pipelined ADC is replaced by the energy efficient SAR ADC. By taking the advantages of the pipelined ADC with high speed and high resolution and the SAR ADC with low power consumption.|
1. Using only two stages in the proposed ADC architecture, and reduce the requirement of power hungry operation amplifier. Removing the front-end sample-and-hold circuit by capacitor array in the SAR ADCs and sample switch. Hence, the whole circuit only requires one operation amplifier which uses in MDAC circuit.
2. The comparators in the proposed ADC are dynamic comparators which consume no static power consumption. Capacitor arrays used in the SAR ADC adopt the monotonic switching procedure to achieve energy efficient and high speed applications.
3. An additional comparator for MSB is designed for the ADC using in sample phase. It can enhance the sample rate of ADC and relax the design difficulty of the operation amplifier in MDAC.
4. A capacitor array combined two kinds of capacitor array is proposed for pipelined-SAR ADC application.
||Shen-Fu Hsiao - chair|
Yun-nan Chang - co-chair
Ko-Chi Kuo - co-chair
Shiann-Rong Kuang - co-chair
Hsiao-Chin Chen - co-chair
Ko-Chi Kuo - advisor
Indicate in-campus at 5 year and off-campus access at 5 year.|
|Date of Submission