|Author's Email Address
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|Type of Document
||IC Design and Implementation of Fast Tagged Sorter and Dynamic 64-Bit Comparator|
|Date of Defense
Power Demand Monitor System
|| Three different topics associated with their respective applications are proposed in this thesis. The first application is the implementation of a fast tagged sorter. A novel and high-speed realization of the tagged sorting algorithm is presented. Meanwhile, the problems to detect whether the queue is empty or full is also resolved without increasing any hardware cost.|
The second topic is focused on the implementation of a fast dynamic 64-bit comparator with small transistor count. The entire 64-bit comparator is composed of equality comparators and zero/one detectors, which are proposed by C.-F. Wu. The problem to handle a large fan-in requirement is also resolved in our design.
The third topic is to carry out a power demand monitor system for factories. Not only can it monitor the factory’s power network with a graphical user interface, but also can turn off the unessential equipments automatically when the total power consumed by the factory is larger than what was expected.
||Sying-Jyan Wang - co-chair|
Yau-Hwang Kuo - co-chair
Chua-Chin Wang - advisor
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|Date of Submission