Title page for etd-0623100-173156


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URN etd-0623100-173156
Author Hsin-Long Wu
Author's Email Address m8731609@student.nsysu.edu.tw
Statistics This thesis had been viewed 5592 times. Download 2994 times.
Department Electrical Engineering
Year 1999
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title IC Design and Implementation of Fast Tagged Sorter and Dynamic 64-Bit Comparator
Date of Defense 2000-06-06
Page Count 71
Keyword
  • Tagged Sorter
  • Power Demand Monitor System
  • Comparator
  • Abstract  Three different topics associated with their respective applications are proposed in this thesis. The first application is the implementation of a fast tagged sorter. A novel and high-speed realization of the tagged sorting algorithm is presented. Meanwhile, the problems to detect whether the queue is empty or full is also resolved without increasing any hardware cost.
     The second topic is focused on the implementation of a fast dynamic 64-bit comparator with small transistor count. The entire 64-bit comparator is composed of equality comparators and zero/one detectors, which are proposed by C.-F. Wu. The problem to handle a large fan-in requirement is also resolved in our design.
     The third topic is to carry out a power demand monitor system for factories. Not only can it monitor the factory’s power network with a graphical user interface, but also can turn off the unessential equipments automatically when the total power consumed by the factory is larger than what was expected.
    Advisory Committee
  • Sying-Jyan Wang - co-chair
  • Yau-Hwang Kuo - co-chair
  • Chua-Chin Wang - advisor
  • Files
  • 論文.pdf
  • indicate access worldwide
    Date of Submission 2000-06-23

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