Title page for etd-0622115-183859


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URN etd-0622115-183859
Author Meng-hsun Chung
Author's Email Address No Public.
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Department Computer Science and Engineering
Year 2014
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC
Date of Defense 2015-06-26
Page Count 71
Keyword
  • Analog-to-Digital Converter
  • ADC
  • Binary-Search ADC
  • Successive Approximation
  • SAR ADC
  • Time-Interleaved
  • Non-overlapping circuit
  • Abstract In this thesis, a 10-bit binary search assisted time-interleaved SAR ADC operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt TSMC 90nm process and can be used for receiving in front-end chip of wireless communication system.
    In circuit design, we take BS-ADC and SAR-ADC’s advantage for the requirement of high sampling rate and low power consumption and separate ADC in two stages. The first stage is Binary-search ADC which converts high five bit at 250Ms/s sampling rate. Due to additional switching circuit to select correct reference voltage, the need of comparators in BS-ADC can be substantially reduced. The second stage is two-channel SAR ADCs which convert low five bit. Each channel operates at 125Ms/s. In binary-weight capacitor array, we give half-reference voltage for LSB capacitor switching with monotonic switching method. Compared to conventional binary-weight capacitor array, the proposed architecture can reduce total capacitance by 75%. The entire architecture is designed in fully-differential circuit to reduce common mode noise and improve the linearity of the circuit.
    Advisory Committee
  • Tong-Yu Hsieh - chair
  • Shu-Min Li - co-chair
  • Shiann-Rong Kuang - co-chair
  • Ko-Chi Kuo - advisor
  • Files
  • etd-0622115-183859.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2015-07-29

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