Title page for etd-0620116-101925


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URN etd-0620116-101925
Author Tai-Feng Chen
Author's Email Address No Public.
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Department Computer Science and Engineering
Year 2015
Semester 2
Degree Master
Type of Document
Language English
Title A Multi-Dimension Signature Compaction Method for
Efficient SoC Error Identification
Date of Defense 2015-10-23
Page Count 46
Keyword
  • Multiple Signature Compaction Method
  • Signature Based Tracing Methodology
  • System-on-a-Chip(SoC)
  • Abstract Signature is an effective lossy compression method to reduce signal trace size at the possible cost of trace precision and implementation cost for different kinds of signatures to generate. In this paper we first investigate how it actually affects the debug flow when we use signatures, and then we examine the strengths and challenges of some typical signature methods. We then further investigate the possibility of combining multiple signatures together to achieve higher Buggy-Cycle-Density (BCD, a metric we proposed to evaluate the trace precision) along with compression ratio, aliasing probability and possible hardware costs. We also proposed a simulation based estimation tool for user to decide which kind of option and scenario they would like to adopt, according to the constraints and requirements that user wanted to meet. With the estimation tool and conditions user provides, they can select the most suitable options to implement on their system. Finally, fitting in the scenario options we acquired above, we implemented a feasible 3D signature compaction method with various debug configurations to justify our work.
    Advisory Committee
  • Chung-Ho Chen - chair
  • Chi-Feng Wu - co-chair
  • Xin-Yu Shih - co-chair
  • Fu-Ching Yang - co-chair
  • Yeong-Kang Lai - co-chair
  • Ing-Jer Huang - advisor
  • Files
  • etd-0620116-101925.pdf
  • Indicate in-campus at 0 year and off-campus access at 3 year.
    Date of Submission 2016-07-22

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